1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which 1T1C memory cells are arranged in a matrix form on a semiconductor substrate.
2. Description of the Background Art
A ferroelectric memory is a nonvolatile memory that allows for fast write at low voltages, and is capable of retaining its data even when the power is turned off. Thus, the ferroelectric memory has started to be applied to data storage devices that require fast data rewrite and low power consumption operation, as a substitute for a device composed of SRAM and a battery.
In recent years, an attempt has been made to produce larger capacity, smaller ferroelectric memories. An example of large-capacity ferroelectric memories includes a ferroelectric memory employing the so-called 1T1C cells. The 1T1C cell consists of one transistor and one capacitor and stores one bit of data. On the other hand, a commonly-used 2T2C cell stores one bit of data with two transistors and two capacitors. Thus, a ferroelectric memory employing 1T1C cells can offer a capacity about twice that of a ferroelectric memory employing 2T2C cells, with equal size (see, for example, “IC memory that does not lose its data—all about FRAM—(Kienai IC memory—FRAM no subete —)”, by Tomoji Kawai, page 29, Kogyo Chosakai Publishing Co., Ltd., Japan, Jun. 22, 1998, Second Impression of the First Edition).
The operation of evaluating data in a ferroelectric memory employing 11C cells will be briefly described below. The ferroelectric memory employing 11C cells uses a reference potential to evaluate data. The reference potential is the mid-potential between the potential of a bit line obtained when reading data “1” from a memory cell and the potential of a bit line obtained when reading data “0” from a memory cell.
When reading data from a memory cell, first, the potential of the memory cell is read through a first bit line to which the memory cell is connected. Then, a reference potential is read through a second bit line which is a counterpart of the first bit line. The difference between the potential of the first bit line and the reference potential of the second bit line is amplified by a sense amplifier to which the first and second bit lines are connected. If the output of the sense amplifier is positive, the data stored in the memory cell is evaluated as “1”. If the output of the sense amplifier is negative, the data stored in the memory cell is evaluated as “0”.
Note that the output of the sense amplifier is positive when the potential of the first bit line is higher than the reference potential, or when the output voltage of the sense amplifier is in the neighborhood of the power supply voltage, or when the output voltage of the sense amplifier is relatively high compared to the output voltage of the sense amplifier when the output is negative. The output of the sense amplifier is negative when the potential of the first bit line is lower than the reference potential, or when the output voltage of the sense amplifier is in the neighborhood of the ground voltage, or when the output voltage of the sense amplifier is relatively low compared to the output voltage of the sense amplifier when the output is positive.
As techniques for generating the reference potential, a dummy cell technique is widely used (see, for example, “IC memory that does not lose its data—all about FRAM—(Kienai IC memory—FRAM no subete—)”, by Tomoji Kawai, page 33, Kogyo Chosakai Publishing Co., Ltd., Japan, Jun. 22, 1998, Second Impression of the First Edition). The dummy cell technique is as follows. Data “1” and data “0” are previously written to two memory cells, respectively (hereinafter referred to as the “reference cells”) which have the same structure as memory cells for storing data. The potentials of the reference cells are read through two bit lines. Finally, an equalization circuit takes the average of the potentials obtained through the two bit lines, thereby generating a reference potential. By this, the reference potential which is the mid-potential between the potential of data “0” and the potential of data “1” can be obtained.
FIG. 4 is a diagram illustrating the entire configuration of a conventional semiconductor memory device. The reference cells are memory cells used to generate a reference potential which serves as the reference for data evaluation, and thus needs to generate stable potentials. Therefore, reference cells 104 are arranged in the central part of a memory cell region 101 where memory cells 102 have a stable periodic pattern, i.e., a shaded part 103 shown in FIG. 4 (see International Publication No. WO 97/36300). This minimizes variations in characteristics between the reference cells 104, allowing to obtain stable reference potentials.
In order to reduce the size of a ferroelectric memory, the bit lines may be multi-layered. The technique for reducing the size of a ferroelectric memory will be described below with reference to a drawing. FIG. 5 is a diagram illustrating two bit lines arranged in the same layer; and two bit lines arranged in different layers.
FIG. 5A is a diagram illustrating wiring in which two bit lines 201 and 202 are arranged in the same layer. The two bit lines 201 and 202 need to be arranged with some space therebetween so as to prevent the adverse effects of noise therefrom. Thus, in FIG. 5A, the two bit lines 201 and 202 are arranged with a space L1 therebetween.
On the other hand, as shown in FIG. 5B, when two bit lines 201 and 202 are arranged in different layers, the space between the two bit lines 201 and 202 in a plane can be made to L2 (L1 >L2). Accordingly, it is possible to reduce the size of the ferroelectric memory.
However, when the bit lines 201 and 202 are arranged in different layers, as shown in FIG. 5B, the parasitic capacity generated in the two bit lines may vary between the layers in which the bit lines 201 and 202 are arranged. The variation in parasitic capacity between the bit lines may cause problems such as variation in reference potential.
In order to reduce variation in parasitic capacity, the bit lines may be crossed each other. This technique will be described below with reference to a drawing. FIG. 6 is a diagram illustrating a section (hereinafter referred to as the “cross section”) where two lines arranged in different layers are crossed each other.
The aforementioned technique is as follows. Bit lines form pairs each composed of two adjacent bit lines, and two bit lines in each pair are crossed each other so as to reverse the positions of the two lines. As shown in FIG. 6, a line 301 present in the uppermost layer is connected to a contact 302 which connects between the uppermost layer and the lowermost layer. In the lowermost layer the contact 302 is connected to a line 303. The line 303 is arranged in an oblique direction with respect to the line 301 and connected to a line 304 which is parallel with the line 301 and arranged in the lowermost layer.
Further, a line 401 present in the lowermost layer is connected to a contact 402 which connects between the uppermost layer and the lowermost layer. In the uppermost layer the contact 402 is connected to a line 403. The line 403 is arranged in an oblique direction with respect to the line 401 and connected to a line 404 which is parallel with the line 401 and arranged in the uppermost layer. By connecting the lines and the contacts in the above-described manner, the two bit lines are crossed each other, thereby allowing the positions of the two lines to reverse relative to each other.
As shown in FIG. 6, by reversing the positions of the two bit lines, the two bit lines are each allowed to have a parasitic capacitance generated in the uppermost layer and a parasitic capacitance generated in the lowermost layer. This equalizes the parasitic capacities of the two bit lines, and accordingly problems such as variation in reference potential caused by variation in parasitic capacity between the bit lines can be solved.
Typically, the cross section shown in FIG. 6 is provided near the center of a memory cell region. Therefore, if the aforementioned size reduction technique is employed in a ferroelectric memory having reference cells near the center of a memory cell region, the cross sections and the reference cells will be overlapped with each other. Since the cross section has a complicated configuration compared to other sections of bit lines, if the cross sections and the reference cells are overlapped with each other, the periodic pattern of the reference cells may become unstable. That is, a conventional ferroelectric memory having reference cells arranged in a region near the center of bit lines cannot achieve a reduction in size by arranging the bit lines in different layers.